Hybrid parallel counters - Domino and threshold logic

Copyright © 2004 IEEEParallel counters are the building blocks of partial product reduction tree (PPRT) circuits, which are required for high-performance multiplication. In this paper we will implement novel counters using a hybrid of domino and threshold logic. A test 64 × 64 PPRT using these counters was found to reduce latency by 39% and device count by 38% compared to the domino logic equivalent.Troy D. Townsend, Peter Celinski, Said F. Al-Sarawi and Michael J. Liebel

Logical effort based design exploration of 64-bit adders using a mixed dynamic-CMOS/threshold-logic approach

Copyright © 2004 IEEEThis paper presents the design exploration of CMOS 64-bit adders designed using threshold logic gates based on systematic transistor level delay estimation using Logical Effort (LE). The adders are hybrid designs consisting of domino and the recently proposed Charge Recycling Threshold Logic (CRTL). The delay evaluation is based LE modeling of the delay of the domino and CRTL gates. From the initial estimations, we select the 8-bit sparse carry look-ahead/carry-select scheme. Simulations indicate a delay of less than 5 FO4, which is 1.1 FO4 or 17% faster than the nearest domino design.Peter Celinski, Said Al-Sarawi, Derek Abbott, Sorin Cotofana and Stamatis Vassiliadi

Data converter

Publication Number: WO/2006/056023 International Application No.: PCT/AU2005/001792A high speed optoelectronic analogue to digital converter using threshold logic circuits.Sarros Tony, Al-Sarawi Said and Celinski Pete